-------------------------------------------------------------------------------
-- FILE: tb_fir.vhd
-- DESCRIPTION: This is the testbench that instantiates the filter top structure
--  and handles input/output data streams. It also provides clock and reset signals.
-------------------------------------------------------------------------------

  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  use ieee.std_logic_signed.all;
  use std.textio.all;
  use work.fir_pack.all;

  entity tb_fir is
  end tb_fir;

  architecture behavioral of tb_fir is

    -- FIR-filter top
    component fir_top
  port (
    clk, rst  : in  std_logic;
    fir_in    : in std_logic_vector(INPUT_WIDTH-1 downto 0);
    fir_out   : out std_logic_vector(INPUT_WIDTH+COEFF_WIDTH+M-1 downto 0)
    );
    end component;

    signal clk, rst : std_logic := '0';
    signal x        : std_logic_vector(INPUT_WIDTH-1 downto 0);
    signal y        : std_logic_vector(OUTPUT_WIDTH-1 downto 0);
    
  begin  -- structural

    clk <= not(clk) after PULSEWIDTH;
    rst <= '1'      after RESET_TIME;

    

    -- Device under test (DUT)
    DUT : fir_top
      port map (
        clk => clk,
        rst => rst,
        fir_in   => x,
        fir_out   => y);

    
    -- Process that read and writes values from and to files.
    process
      file fin      : text is in STIMULI_FILE;
      file fout     : text is out TRACE_FILE;
      variable lin  : line;
      variable data : integer;
    begin
      x <= (others => '0');
      loop
        wait until clk = '1' and rst = '1';
        if not (endfile (fin)) then
          readline(fin, lin);
          read(lin, data);
          x <= std_logic_vector (to_signed(data, INPUT_WIDTH)) after DELAY;
        else
          x <= (others => '0');
        end if;
        data := conv_integer (y);
        write (lin, data);
        writeline (fout, lin);
      end loop;
    end process;
    



  end behavioral;
